A high breakdown voltage power device fabricated with SiC has the potential of significantly reducing the on-state-resistance. For example, according to the press release from Rohm Co., Ltd., an SiC MOSFET (a Field Effect Transistor with a Metal-Oxide-Semiconductor structure) to be mass-produced by Rohm Co., Ltd. is to have its on-state-resistance becoming a half the on-state-resistance of an Si IGBT (Insulated Gate Bipolar Transistor) having the same breakdown voltage class. See An SiC power MOSFET has been developed with a less power loss of 1/40 of conventional one!” at http://www.rohm.co.jp/news/sicpower-j.html, circa Jun. 30, 2005.
A high breakdown voltage MOSFET of SiC as a principal material thereof is expected to be shipped from each semiconductor device maker within the next one or two years. In the future, most of IGBTs of Si as inverter parts are expected to be substituted by IGBTs of SiC, while reducing the cost and improving their electrical characteristics. Mass producing SiC devices, however, can be problematic in that an SiC wafer is very expensive in comparison with an Si wafer. Presently, the unit price per unit area of an SiC wafer is several tens of times the unit price per unit area of an Si wafer. Therefore, at the development of a SiC device, it is very important to enhance the current driving capability per unit area.
Currently, the condition at the SiO2/SiC interface is not so good as the condition at the SiO2/Si interface. Therefore, the carrier mobility in its MOS channel at the SiO2/SiC interface is on the order of several tens cm2/Vs, which is approximately one order smaller than the carrier mobility in its MOS channel at the SiO2/Si interface. Therefore, in a high breakdown voltage device of SiC, it is important to reduce the on-state-resistance due to its MOS channel.
Moreover, in an SiC device, the resistance in its drift region is very small in comparison with that in an Si device. This makes the resistance in the MOS channel (channel resistance) occupy most of the resistance in the device. Therefore, the current driving capability of an SiC device is determined mainly by the channel density per unit area of the device.
The structures of vertical MISFETs, such as vertical MOSFETs, can be roughly classified into DMOSFET types (an example of which is shown in FIG. 15) and trench MOSFET types (an example of which is show in FIG. 16). In each of the figures, reference numeral 1 denotes a substrate, which is to be a drain region. Reference numerals 2, 3, 4, 5, 6, 7, 8, 9 and 10 denote a drift layer, a body region, a source contact region, a body contact region, a gate oxide film, a gate electrode, an interlayer insulator film, a source electrode and a drain electrode, respectively. In FIG. 16, reference numeral 11 denotes a trench.
In each of FIG. 15 and FIG. 16, a structure having one gate electrode is shown as a unit structure. In an actual device, however, many of the unit structures are repeatedly arranged. These figures are not drawn to an actual scale (which would only show a hairline when drawn in an actual scale) but is exaggeratedly illustrated with a scale different from the actual for illustration purposes (the same applies to other drawings). Moreover, the same or similar elements are designated with the same reference numerals with redundant explanation thereof omitted.
As show in FIG. 15, in a DMOSFET type, in the on-state, electrons, having passed through a MIS (“MOS” when the insulator film 6 is an oxide film) channel 12 formed at the interface with the gate oxide film 6 in the body region 3, flow in a JFET region 13 between the body regions 3 to the substrate 1 through the drift layer 2. In the off-state, the JFET region 13 basically comes to a pinch-off state with most part of the applied voltage carried by its p-n junction between the body region 3 and the drift layer 2. Therefore, at around the gate electrode 6, the electric field strength is considerably reduced.
In the structure shown in FIG. 15, however, the presence of p-n junctions on both sides of the JFET region 13 causes a depletion layer to extend from each of the p-n junctions toward the JFET region 13 by the length corresponding to the built-in voltage of each of the p-n junctions, forming a narrowed current path. This increases the resistance in the JFET region 13 (hereinafter referred to as “JFET resistance”).
Reducing the width of the unit structure shown in FIG. 15, i.e., reducing the cell pitch, for enhancing the current driving capability per unit area reduces the width of the JFET region 13. However, the amount of narrowing in the current path due to the JFET effect is left unchanged. This reduces the proportion of the section with no narrowed current path in the JFET region 13, increasing the JFET resistance.
Such increase in the JFET resistance is unfavorable because it increases the loss in the on-state. Moreover, a too narrow width of the JFET region 13 pinches off the JFET region 13 by the built-in potential of each of the p-n junctions, which causes an abrupt increase in the JFET resistance. Therefore, there is a certain lower limit in the width of the JFET region 13, which also limits the lowest cell pitch.
The trench MOSFET type shown in FIG. 16, however, has no JFET region. Thus, in the on-state, electrons having passed through the MIS (MOS) channel 12 immediately enter the drift layer 2 to reach the substrate 1. Such absence of a JFET region provides no JFET resistance, which allows reduction in the cell pitch more than that of the DMOSFET type. Therefore, in the trench MOSFET type, the current driving capability per unit area can be enhanced more than in the DMOSFET type.
In the trench MOSFET type structure, in the off-state, the electric field strength becomes the highest in the vicinity of the interface of the p-n junction formed of the body region 3 and the drift layer 2. Moreover, in the off-state, an electric flux enters into an insulator film between the gate electrode 7 and the drift layer 2 at the bottom of the trench 11 with the density approximately equal to the density of the electric flux in the vicinity of the p-n junction formed of the body region 3 and the drift layer 2. Here, what becomes equal in all of the semiconductor and the insulator film is not the electric field strength but the electric flux density or a product of relative permittivity and electric field strength (hereinafter referred to as “electric field strength and relative permittivity product”).
In Si, the insulation breakdown electric field strength is on the order of 0.3 MV/cm and its relative permittivity is on the order of 12. In SiO2, which is mainly used as an insulator film, the normal value of the insulation breakdown electric field strength (hereinafter referred to as “normal insulation breakdown electric field strength”) is 2.5 to 3 MV/cm and its relative permittivity is approximately a little less than 4. Therefore, when using Si as a semiconductor, the electric field strength and relative permittivity product due to the electric flux entering into the SiO2 as an insulator film is less than 3.6 MV/cm unless electric field crowding occurs. This value corresponds to approximately on the order of 1 MV/cm or less in electric field strength, which causes no particular problem.
Here, the reason for using a normal insulation breakdown electric field strength about SiO2 is as follows. An insulator, in particular an insulator in an amorphous state such as SiO2 used in a semiconductor process, does not breakdown even though an electric field with high strength is instantaneously applied thereto. However, an electric field with high strength applied to the insulator for a long time deteriorates the insulator gradually over time until it eventually breaks down.
Therefore, to ensure that the insulator functions for a specified device life time, the design of the device must be carried out with a specified electric field strength, lower than the instantaneous insulation breakdown electric field strength, determined as an upper limit, so that no electric field with strength higher than the upper limit is applied to the insulator. Thus, the specified electric field strength lower than the instantaneous insulation breakdown electric field strength is used for the design basis as the normal insulation breakdown electric field strength.
To avoid electric field crowding in Si, a structure where SiO2 is made to share an applied voltage (as in the example shown in FIG. 17) has been proposed. See Masahito Kodama, et al., Temperature characteristics of a new 100V rated power MOSFET, VLMOS (Vertical LOCOS MOS)”, Proceedings of 2004 International Symposium on Power Semiconductor Devices & ICs, pp. 463-466 (2004). In the structure shown in FIG. 17, the trench 11 is formed deep to reach the substrate 1. Moreover, a RESURF structure is formed so that a thick SiO2 field insulator film 14 isolates the gate electrode 7 from the substrate 1 and the drift layer 2. About the field insulator film 14, the gate electrode 7 and the substrate 1 (as a drain region) are made obviously close to each other. This makes it evident that an electric field is applied to the SiO2 with a higher strength in comparison with the strength of the electric field applied to the Si.
In general, in a power device, when the device suffers a breakdown by an overvoltage, it is necessary to avoid a short circuit between the gate and the drain that occurs without the source and the drain being short-circuited. The reason is as follows. Normally, in each of high voltage circuits on the source and drain sides, measures are taken against the short circuit between the source and the drain. Therefore, should the source and the drain be short-circuited, only the device is burnt out, or only a few other power devices operating in cooperation with the device or only passive elements are burnt out. In comparison, in a control circuit on the gate side, the breakdown voltage thereof is generally low. Therefore, when a high voltage on the drain side is applied to the gate by a short circuit between the gate and the drain, the control circuit on the gate side become damaged. Then, the destructive high voltage is transmitted from the control circuit to the neighboring low voltage circuits from one to another to possibly causing fatal damages of the entire system using the power device. To prevent such a situation, it is possible to add a Zener diode with a sufficiently large capacity to the gate circuit. This, however, is not only economically undesirable but also decreases performance, such as by increasing the switching loss, reducing the switching speed, and distorting the control signal waveform due to charge and discharge of the Zener diode carried out at each switching.
Thus, it is not desirable to incorporate such a design where the breakdown voltage of the device is determined by the breakdown voltage between the gate and the drain. To ensure a sufficiently high breakdown voltage between the gate and the drain, it is necessary for the device to have such a device structure where a high breakdown voltage between the gate and the drain can be ensured even in the case where the insulation breakdown electric field strength of the semiconductor is considerably high.
Incidentally, the reason for enabling a significant reduction in the on-state-resistance using SiC is as follows. Since the insulation breakdown electric field strength of SiC is higher than that of Si, an SiC device, brought into realization with a breakdown voltage being the same as that of a Si device, is allowed to have a drift layer thinner than that of the Si device. Moreover, the amount of doping in the drift layer in the SiC device can be made higher than that in the Si device. Thus, the resistance of the drift layer in the SiC device can be reduced by two orders or more in comparison with that of the Si device.
However, a vertical trench MISFET using SiC, otherwise having the same structure as the Si device as shown in FIG. 16 causes the following problem. SiC has a relative permittivity on the order of 9.6 to 10, which is not much different from that of Si. In comparison, the insulation breakdown electric field strength of SiC is 1.5 to 2.5 MV/cm, which is 5 to 8 times higher than that of Si. Thus, from the value of the electric field strength and relative permittivity product in the SiO2 insulator film at the bottom of the trench 11 in the structure as shown in FIG. 16, it is known that an electric field with excessive strength is to be applied to the SiO2 insulator film.
Therefore, the breakdown voltage of the device is determined by the normal insulation breakdown electric field strength of the insulator film at the bottom of the trench 11 rather than the breakdown voltage of the p-n junction formed of the body region 3 and the drift layer 2. As a solution to this problem, a structure as in the example shown in FIG. 18 is known, where, when the drift layer 2 is an n-type, a buried p-type region 15 is provided at the bottom of the trench 11 so that the buried p-type region 15 is kept at the source potential. See for example U.S. Pat. No. 6,180,958.
As another structure for avoiding an electric field with excessive strength from being applied to the insulator film at the bottom of the trench, proposes increasing the thickness of the insulator film at the bottom of the trench. See for example JP-A-2-102579 and JP-A-7-326755). Other solutions include lowering the breakdown voltage of the p-n junction diode formed mainly of a body region and a drift region, and causing electric field crowding in the section other than the bottom of the trench. See for example JP-A-10-308512.
In the structure shown in FIG. 18, however, the p-n junction formed with the buried p-type region 15 and the drift region 2 causes a depletion layer to extend into the drift layer 2 by a length approximately corresponding to the built-in potential of the p-n junction. As a result, the current path is narrowed, increasing the resistance of the device. This is essentially the same as the JFET effect in principle. Namely, the buried p-type region 15 provided at the bottom of the trench causes the JFET effect, which should have been avoided by employing the trench MOSFET type structure. This, like in the case in the DMOSFET structure, imposes limitation on reducing the cell pitch. Therefore, as was explained above, in an SiC device using an expensive SiC wafer, despite the importance of cell pitch reduction, the main effect of reducing the cell pitch, which is obtained by providing the trench MOSFET type structure, is lost.
Moreover, in each of the structures disclosed in JP-A-2-102579 and JP-A-7-326755, the breakdown voltage thereof is limited by the electric field strength in the insulator film at the bottom of the trench rather than the electric field strength in SiC. Thus, it cannot be said that a full use is made of a high value of the insulation breakdown electric field strength of SiC. Furthermore, the structure disclosed in JP-A-10-308512 has a drawback in that it prevents realization of a high breakdown voltage expected from the high value of the insulation breakdown electric field strength of SiC.
Accordingly, there remains a need for a semiconductor device that can avoid the above-explained problems and inhibit a short circuit between a gate and a drain due to breakage of the insulator film at the bottom of a trench, to enable realization of a high breakdown voltage. The present invention addresses this need.